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nvic.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
3/*
4 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _HARDWARE_STRUCTS_NVIC_H
10#define _HARDWARE_STRUCTS_NVIC_H
11
13#include "hardware/regs/m0plus.h"
14
15// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
16//
17// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
18// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
19//
20// Bit-field descriptions are of the form:
21// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
22
23typedef struct {
24 _REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER
25 // Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled
26 // 0xffffffff [31:0] : SETENA (0): Interrupt set-enable bits
27 io_rw_32 iser;
28
29 uint32_t _pad0[31];
30
31 _REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER
32 // Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled
33 // 0xffffffff [31:0] : CLRENA (0): Interrupt clear-enable bits
34 io_rw_32 icer;
35
36 uint32_t _pad1[31];
37
38 _REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR
39 // The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending
40 // 0xffffffff [31:0] : SETPEND (0): Interrupt set-pending bits
41 io_rw_32 ispr;
42
43 uint32_t _pad2[31];
44
45 _REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR
46 // Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending
47 // 0xffffffff [31:0] : CLRPEND (0): Interrupt clear-pending bits
48 io_rw_32 icpr;
49
50 uint32_t _pad3[95];
51
52 _REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0
53 // (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes)
54 //
55 // Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts
56 // 0xc0000000 [31:30] : IP_3 (0): Priority of interrupt 3
57 // 0x00c00000 [23:22] : IP_2 (0): Priority of interrupt 2
58 // 0x0000c000 [15:14] : IP_1 (0): Priority of interrupt 1
59 // 0x000000c0 [7:6] : IP_0 (0): Priority of interrupt 0
60 io_rw_32 ipr[8];
61} nvic_hw_t;
62
63#define nvic_hw ((nvic_hw_t *)(PPB_BASE + M0PLUS_NVIC_ISER_OFFSET))
64
65#endif
Definition nvic.h:23