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iobank0.h
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/*
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_IOBANK0_H
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#define _HARDWARE_STRUCTS_IOBANK0_H
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#include "
hardware/address_mapped.h
"
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#include "hardware/regs/io_bank0.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
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typedef
struct
{
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_REG_(IO_BANK0_GPIO0_STATUS_OFFSET)
// IO_BANK0_GPIO0_STATUS
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// GPIO status
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// 0x04000000 [26] : IRQTOPROC (0): interrupt to processors, after override is applied
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// 0x01000000 [24] : IRQFROMPAD (0): interrupt from pad before override is applied
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// 0x00080000 [19] : INTOPERI (0): input signal to peripheral, after override is applied
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// 0x00020000 [17] : INFROMPAD (0): input signal from pad, before override is applied
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// 0x00002000 [13] : OETOPAD (0): output enable to pad after register override is applied
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// 0x00001000 [12] : OEFROMPERI (0): output enable from selected peripheral, before register override is applied
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// 0x00000200 [9] : OUTTOPAD (0): output signal to pad after register override is applied
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// 0x00000100 [8] : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied
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io_ro_32 status;
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_REG_(IO_BANK0_GPIO0_CTRL_OFFSET)
// IO_BANK0_GPIO0_CTRL
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// GPIO control including function select and overrides
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// 0x30000000 [29:28] : IRQOVER (0)
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// 0x00030000 [17:16] : INOVER (0)
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// 0x00003000 [13:12] : OEOVER (0)
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// 0x00000300 [9:8] : OUTOVER (0)
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// 0x0000001f [4:0] : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table
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io_rw_32 ctrl;
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}
iobank0_status_ctrl_hw_t
;
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typedef
struct
{
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_REG_(IO_BANK0_PROC0_INTE0_OFFSET)
// IO_BANK0_PROC0_INTE0
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// (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes)
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//
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// Interrupt Enable for proc0
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// 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
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// 0x40000000 [30] : GPIO7_EDGE_LOW (0)
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// 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
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// 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
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// 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
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// 0x04000000 [26] : GPIO6_EDGE_LOW (0)
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// 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
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// 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
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// 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
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// 0x00400000 [22] : GPIO5_EDGE_LOW (0)
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// 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
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// 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
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// 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
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// 0x00040000 [18] : GPIO4_EDGE_LOW (0)
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// 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
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// 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
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// 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
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// 0x00004000 [14] : GPIO3_EDGE_LOW (0)
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// 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
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// 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
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// 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
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// 0x00000400 [10] : GPIO2_EDGE_LOW (0)
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// 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
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// 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
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// 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
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// 0x00000040 [6] : GPIO1_EDGE_LOW (0)
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// 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
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// 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
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// 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
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// 0x00000004 [2] : GPIO0_EDGE_LOW (0)
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// 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
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// 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
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io_rw_32 inte[4];
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_REG_(IO_BANK0_PROC0_INTF0_OFFSET)
// IO_BANK0_PROC0_INTF0
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// (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes)
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//
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// Interrupt Force for proc0
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// 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
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// 0x40000000 [30] : GPIO7_EDGE_LOW (0)
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// 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
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// 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
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// 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
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// 0x04000000 [26] : GPIO6_EDGE_LOW (0)
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// 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
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// 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
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// 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
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// 0x00400000 [22] : GPIO5_EDGE_LOW (0)
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// 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
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// 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
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// 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
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// 0x00040000 [18] : GPIO4_EDGE_LOW (0)
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// 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
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// 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
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// 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
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// 0x00004000 [14] : GPIO3_EDGE_LOW (0)
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// 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
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// 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
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// 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
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// 0x00000400 [10] : GPIO2_EDGE_LOW (0)
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// 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
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// 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
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// 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
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// 0x00000040 [6] : GPIO1_EDGE_LOW (0)
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// 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
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// 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
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// 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
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// 0x00000004 [2] : GPIO0_EDGE_LOW (0)
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// 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
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// 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
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io_rw_32 intf[4];
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_REG_(IO_BANK0_PROC0_INTS0_OFFSET)
// IO_BANK0_PROC0_INTS0
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// (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes)
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//
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// Interrupt status after masking & forcing for proc0
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// 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
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// 0x40000000 [30] : GPIO7_EDGE_LOW (0)
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// 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
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// 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
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// 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
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// 0x04000000 [26] : GPIO6_EDGE_LOW (0)
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// 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
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// 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
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// 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
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// 0x00400000 [22] : GPIO5_EDGE_LOW (0)
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// 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
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// 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
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// 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
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// 0x00040000 [18] : GPIO4_EDGE_LOW (0)
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// 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
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// 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
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// 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
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// 0x00004000 [14] : GPIO3_EDGE_LOW (0)
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// 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
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// 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
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// 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
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// 0x00000400 [10] : GPIO2_EDGE_LOW (0)
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// 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
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// 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
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// 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
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// 0x00000040 [6] : GPIO1_EDGE_LOW (0)
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// 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
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// 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
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// 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
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// 0x00000004 [2] : GPIO0_EDGE_LOW (0)
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// 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
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// 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
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io_ro_32 ints[4];
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}
io_irq_ctrl_hw_t
;
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typedef
struct
{
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iobank0_status_ctrl_hw_t
io[NUM_BANK0_GPIOS];
// 30
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_REG_(IO_BANK0_INTR0_OFFSET)
// IO_BANK0_INTR0
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// (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes)
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//
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// Raw Interrupts
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// 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
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// 0x40000000 [30] : GPIO7_EDGE_LOW (0)
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// 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
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// 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
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// 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
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// 0x04000000 [26] : GPIO6_EDGE_LOW (0)
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// 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
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// 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
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// 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
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// 0x00400000 [22] : GPIO5_EDGE_LOW (0)
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// 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
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// 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
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// 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
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// 0x00040000 [18] : GPIO4_EDGE_LOW (0)
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// 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
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// 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
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// 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
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// 0x00004000 [14] : GPIO3_EDGE_LOW (0)
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// 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
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// 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
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// 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
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// 0x00000400 [10] : GPIO2_EDGE_LOW (0)
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// 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
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// 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
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// 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
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// 0x00000040 [6] : GPIO1_EDGE_LOW (0)
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// 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
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// 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
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// 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
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// 0x00000004 [2] : GPIO0_EDGE_LOW (0)
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// 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
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// 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
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io_rw_32 intr[4];
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io_irq_ctrl_hw_t
proc0_irq_ctrl;
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io_irq_ctrl_hw_t
proc1_irq_ctrl;
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io_irq_ctrl_hw_t
dormant_wake_irq_ctrl;
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}
iobank0_hw_t
;
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#define iobank0_hw ((iobank0_hw_t *)IO_BANK0_BASE)
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static_assert
( NUM_BANK0_GPIOS == 30,
""
);
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#endif
address_mapped.h
io_irq_ctrl_hw_t
Definition
iobank0.h:46
iobank0_hw_t
Definition
iobank0.h:163
iobank0_status_ctrl_hw_t
Definition
iobank0.h:23