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clocks.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
3/*
4 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _HARDWARE_STRUCTS_CLOCKS_H
10#define _HARDWARE_STRUCTS_CLOCKS_H
11
13#include "hardware/regs/clocks.h"
14
15// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks
16//
17// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
18// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h.
19//
20// Bit-field descriptions are of the form:
21// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
22
41
43typedef struct {
44 _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL
45 // Clock control, can be changed on-the-fly (except for auxsrc)
46 // 0x00100000 [20] : NUDGE (0): An edge on this signal shifts the phase of the output by 1 cycle of the input clock
47 // 0x00030000 [17:16] : PHASE (0): This delays the enable signal by up to 3 cycles of the input clock
48 // 0x00001000 [12] : DC50 (0): Enables duty cycle correction for odd divisors
49 // 0x00000800 [11] : ENABLE (0): Starts and stops the clock generator cleanly
50 // 0x00000400 [10] : KILL (0): Asynchronously kills the clock generator
51 // 0x000001e0 [8:5] : AUXSRC (0): Selects the auxiliary clock source, will glitch when switching
52 io_rw_32 ctrl;
53
54 _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV
55 // Clock divisor, can be changed on-the-fly
56 // 0xffffff00 [31:8] : INT (1): Integer component of the divisor, 0 -> divide by 2^16
57 // 0x000000ff [7:0] : FRAC (0): Fractional component of the divisor
58 io_rw_32 div;
59
60 _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED
61 // Indicates which SRC is currently selected by the glitchless mux (one-hot)
62 io_ro_32 selected;
65
66typedef struct {
67 _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL
68 // 0x00010000 [16] : CLEAR (0): For clearing the resus after the fault that triggered it has been corrected
69 // 0x00001000 [12] : FRCE (0): Force a resus, for test purposes only
70 // 0x00000100 [8] : ENABLE (0): Enable resus
71 // 0x000000ff [7:0] : TIMEOUT (0xff): This is expressed as a number of clk_ref cycles
72 io_rw_32 ctrl;
73
74 _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS
75 // 0x00000001 [0] : RESUSSED (0): Clock has been resuscitated, correct the error then send ctrl_clear=1
76 io_ro_32 status;
78
79typedef struct {
80 _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ
81 // Reference clock frequency in kHz
82 // 0x000fffff [19:0] : FC0_REF_KHZ (0)
83 io_rw_32 ref_khz;
84
85 _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ
86 // Minimum pass frequency in kHz
87 // 0x01ffffff [24:0] : FC0_MIN_KHZ (0)
88 io_rw_32 min_khz;
89
90 _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ
91 // Maximum pass frequency in kHz
92 // 0x01ffffff [24:0] : FC0_MAX_KHZ (0x1ffffff)
93 io_rw_32 max_khz;
94
95 _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY
96 // Delays the start of frequency counting to allow the mux to settle
97 // 0x00000007 [2:0] : FC0_DELAY (1)
98 io_rw_32 delay;
99
100 _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL
101 // The test interval is 0
102 // 0x0000000f [3:0] : FC0_INTERVAL (0x8)
103 io_rw_32 interval;
104
105 _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC
106 // Clock sent to frequency counter, set to 0 when not required
107 // 0x000000ff [7:0] : FC0_SRC (0)
108 io_rw_32 src;
109
110 _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS
111 // Frequency counter status
112 // 0x10000000 [28] : DIED (0): Test clock stopped during test
113 // 0x01000000 [24] : FAST (0): Test clock faster than expected, only valid when status_done=1
114 // 0x00100000 [20] : SLOW (0): Test clock slower than expected, only valid when status_done=1
115 // 0x00010000 [16] : FAIL (0): Test failed
116 // 0x00001000 [12] : WAITING (0): Waiting for test clock to start
117 // 0x00000100 [8] : RUNNING (0): Test running
118 // 0x00000010 [4] : DONE (0): Test complete
119 // 0x00000001 [0] : PASS (0): Test passed
120 io_ro_32 status;
121
122 _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT
123 // Result of frequency measurement, only valid when status_done=1
124 // 0x3fffffe0 [29:5] : KHZ (0)
125 // 0x0000001f [4:0] : FRAC (0)
126 io_ro_32 result;
127} fc_hw_t;
128
129typedef struct {
130 clock_hw_t clk[CLK_COUNT]; // 10
131
132 clock_resus_hw_t resus;
133
134 fc_hw_t fc0;
135
136 _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
137 // enable clock in wake mode
138 // 0x80000000 [31] : clk_sys_sram3 (1)
139 // 0x40000000 [30] : clk_sys_sram2 (1)
140 // 0x20000000 [29] : clk_sys_sram1 (1)
141 // 0x10000000 [28] : clk_sys_sram0 (1)
142 // 0x08000000 [27] : clk_sys_spi1 (1)
143 // 0x04000000 [26] : clk_peri_spi1 (1)
144 // 0x02000000 [25] : clk_sys_spi0 (1)
145 // 0x01000000 [24] : clk_peri_spi0 (1)
146 // 0x00800000 [23] : clk_sys_sio (1)
147 // 0x00400000 [22] : clk_sys_rtc (1)
148 // 0x00200000 [21] : clk_rtc_rtc (1)
149 // 0x00100000 [20] : clk_sys_rosc (1)
150 // 0x00080000 [19] : clk_sys_rom (1)
151 // 0x00040000 [18] : clk_sys_resets (1)
152 // 0x00020000 [17] : clk_sys_pwm (1)
153 // 0x00010000 [16] : clk_sys_psm (1)
154 // 0x00008000 [15] : clk_sys_pll_usb (1)
155 // 0x00004000 [14] : clk_sys_pll_sys (1)
156 // 0x00002000 [13] : clk_sys_pio1 (1)
157 // 0x00001000 [12] : clk_sys_pio0 (1)
158 // 0x00000800 [11] : clk_sys_pads (1)
159 // 0x00000400 [10] : clk_sys_vreg_and_chip_reset (1)
160 // 0x00000200 [9] : clk_sys_jtag (1)
161 // 0x00000100 [8] : clk_sys_io (1)
162 // 0x00000080 [7] : clk_sys_i2c1 (1)
163 // 0x00000040 [6] : clk_sys_i2c0 (1)
164 // 0x00000020 [5] : clk_sys_dma (1)
165 // 0x00000010 [4] : clk_sys_busfabric (1)
166 // 0x00000008 [3] : clk_sys_busctrl (1)
167 // 0x00000004 [2] : clk_sys_adc (1)
168 // 0x00000002 [1] : clk_adc_adc (1)
169 // 0x00000001 [0] : clk_sys_clocks (1)
170 io_rw_32 wake_en0;
171
172 _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1
173 // enable clock in wake mode
174 // 0x00004000 [14] : clk_sys_xosc (1)
175 // 0x00002000 [13] : clk_sys_xip (1)
176 // 0x00001000 [12] : clk_sys_watchdog (1)
177 // 0x00000800 [11] : clk_usb_usbctrl (1)
178 // 0x00000400 [10] : clk_sys_usbctrl (1)
179 // 0x00000200 [9] : clk_sys_uart1 (1)
180 // 0x00000100 [8] : clk_peri_uart1 (1)
181 // 0x00000080 [7] : clk_sys_uart0 (1)
182 // 0x00000040 [6] : clk_peri_uart0 (1)
183 // 0x00000020 [5] : clk_sys_timer (1)
184 // 0x00000010 [4] : clk_sys_tbman (1)
185 // 0x00000008 [3] : clk_sys_sysinfo (1)
186 // 0x00000004 [2] : clk_sys_syscfg (1)
187 // 0x00000002 [1] : clk_sys_sram5 (1)
188 // 0x00000001 [0] : clk_sys_sram4 (1)
189 io_rw_32 wake_en1;
190
191 _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
192 // enable clock in sleep mode
193 // 0x80000000 [31] : clk_sys_sram3 (1)
194 // 0x40000000 [30] : clk_sys_sram2 (1)
195 // 0x20000000 [29] : clk_sys_sram1 (1)
196 // 0x10000000 [28] : clk_sys_sram0 (1)
197 // 0x08000000 [27] : clk_sys_spi1 (1)
198 // 0x04000000 [26] : clk_peri_spi1 (1)
199 // 0x02000000 [25] : clk_sys_spi0 (1)
200 // 0x01000000 [24] : clk_peri_spi0 (1)
201 // 0x00800000 [23] : clk_sys_sio (1)
202 // 0x00400000 [22] : clk_sys_rtc (1)
203 // 0x00200000 [21] : clk_rtc_rtc (1)
204 // 0x00100000 [20] : clk_sys_rosc (1)
205 // 0x00080000 [19] : clk_sys_rom (1)
206 // 0x00040000 [18] : clk_sys_resets (1)
207 // 0x00020000 [17] : clk_sys_pwm (1)
208 // 0x00010000 [16] : clk_sys_psm (1)
209 // 0x00008000 [15] : clk_sys_pll_usb (1)
210 // 0x00004000 [14] : clk_sys_pll_sys (1)
211 // 0x00002000 [13] : clk_sys_pio1 (1)
212 // 0x00001000 [12] : clk_sys_pio0 (1)
213 // 0x00000800 [11] : clk_sys_pads (1)
214 // 0x00000400 [10] : clk_sys_vreg_and_chip_reset (1)
215 // 0x00000200 [9] : clk_sys_jtag (1)
216 // 0x00000100 [8] : clk_sys_io (1)
217 // 0x00000080 [7] : clk_sys_i2c1 (1)
218 // 0x00000040 [6] : clk_sys_i2c0 (1)
219 // 0x00000020 [5] : clk_sys_dma (1)
220 // 0x00000010 [4] : clk_sys_busfabric (1)
221 // 0x00000008 [3] : clk_sys_busctrl (1)
222 // 0x00000004 [2] : clk_sys_adc (1)
223 // 0x00000002 [1] : clk_adc_adc (1)
224 // 0x00000001 [0] : clk_sys_clocks (1)
225 io_rw_32 sleep_en0;
226
227 _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1
228 // enable clock in sleep mode
229 // 0x00004000 [14] : clk_sys_xosc (1)
230 // 0x00002000 [13] : clk_sys_xip (1)
231 // 0x00001000 [12] : clk_sys_watchdog (1)
232 // 0x00000800 [11] : clk_usb_usbctrl (1)
233 // 0x00000400 [10] : clk_sys_usbctrl (1)
234 // 0x00000200 [9] : clk_sys_uart1 (1)
235 // 0x00000100 [8] : clk_peri_uart1 (1)
236 // 0x00000080 [7] : clk_sys_uart0 (1)
237 // 0x00000040 [6] : clk_peri_uart0 (1)
238 // 0x00000020 [5] : clk_sys_timer (1)
239 // 0x00000010 [4] : clk_sys_tbman (1)
240 // 0x00000008 [3] : clk_sys_sysinfo (1)
241 // 0x00000004 [2] : clk_sys_syscfg (1)
242 // 0x00000002 [1] : clk_sys_sram5 (1)
243 // 0x00000001 [0] : clk_sys_sram4 (1)
244 io_rw_32 sleep_en1;
245
246 _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
247 // indicates the state of the clock enable
248 // 0x80000000 [31] : clk_sys_sram3 (0)
249 // 0x40000000 [30] : clk_sys_sram2 (0)
250 // 0x20000000 [29] : clk_sys_sram1 (0)
251 // 0x10000000 [28] : clk_sys_sram0 (0)
252 // 0x08000000 [27] : clk_sys_spi1 (0)
253 // 0x04000000 [26] : clk_peri_spi1 (0)
254 // 0x02000000 [25] : clk_sys_spi0 (0)
255 // 0x01000000 [24] : clk_peri_spi0 (0)
256 // 0x00800000 [23] : clk_sys_sio (0)
257 // 0x00400000 [22] : clk_sys_rtc (0)
258 // 0x00200000 [21] : clk_rtc_rtc (0)
259 // 0x00100000 [20] : clk_sys_rosc (0)
260 // 0x00080000 [19] : clk_sys_rom (0)
261 // 0x00040000 [18] : clk_sys_resets (0)
262 // 0x00020000 [17] : clk_sys_pwm (0)
263 // 0x00010000 [16] : clk_sys_psm (0)
264 // 0x00008000 [15] : clk_sys_pll_usb (0)
265 // 0x00004000 [14] : clk_sys_pll_sys (0)
266 // 0x00002000 [13] : clk_sys_pio1 (0)
267 // 0x00001000 [12] : clk_sys_pio0 (0)
268 // 0x00000800 [11] : clk_sys_pads (0)
269 // 0x00000400 [10] : clk_sys_vreg_and_chip_reset (0)
270 // 0x00000200 [9] : clk_sys_jtag (0)
271 // 0x00000100 [8] : clk_sys_io (0)
272 // 0x00000080 [7] : clk_sys_i2c1 (0)
273 // 0x00000040 [6] : clk_sys_i2c0 (0)
274 // 0x00000020 [5] : clk_sys_dma (0)
275 // 0x00000010 [4] : clk_sys_busfabric (0)
276 // 0x00000008 [3] : clk_sys_busctrl (0)
277 // 0x00000004 [2] : clk_sys_adc (0)
278 // 0x00000002 [1] : clk_adc_adc (0)
279 // 0x00000001 [0] : clk_sys_clocks (0)
280 io_ro_32 enabled0;
281
282 _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1
283 // indicates the state of the clock enable
284 // 0x00004000 [14] : clk_sys_xosc (0)
285 // 0x00002000 [13] : clk_sys_xip (0)
286 // 0x00001000 [12] : clk_sys_watchdog (0)
287 // 0x00000800 [11] : clk_usb_usbctrl (0)
288 // 0x00000400 [10] : clk_sys_usbctrl (0)
289 // 0x00000200 [9] : clk_sys_uart1 (0)
290 // 0x00000100 [8] : clk_peri_uart1 (0)
291 // 0x00000080 [7] : clk_sys_uart0 (0)
292 // 0x00000040 [6] : clk_peri_uart0 (0)
293 // 0x00000020 [5] : clk_sys_timer (0)
294 // 0x00000010 [4] : clk_sys_tbman (0)
295 // 0x00000008 [3] : clk_sys_sysinfo (0)
296 // 0x00000004 [2] : clk_sys_syscfg (0)
297 // 0x00000002 [1] : clk_sys_sram5 (0)
298 // 0x00000001 [0] : clk_sys_sram4 (0)
299 io_ro_32 enabled1;
300
301 _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR
302 // Raw Interrupts
303 // 0x00000001 [0] : CLK_SYS_RESUS (0)
304 io_ro_32 intr;
305
306 _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE
307 // Interrupt Enable
308 // 0x00000001 [0] : CLK_SYS_RESUS (0)
309 io_rw_32 inte;
310
311 _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF
312 // Interrupt Force
313 // 0x00000001 [0] : CLK_SYS_RESUS (0)
314 io_rw_32 intf;
315
316 _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS
317 // Interrupt status after masking & forcing
318 // 0x00000001 [0] : CLK_SYS_RESUS (0)
319 io_ro_32 ints;
321
322#define clocks_hw ((clocks_hw_t *)CLOCKS_BASE)
323
324static_assert( CLK_COUNT == 10, "");
325
326#endif
clock_index
Enumeration identifying a hardware clock.
Definition clocks.h:27
@ clk_rtc
Real time clock.
Definition clocks.h:37
@ clk_gpout0
GPIO Muxing 0.
Definition clocks.h:28
@ clk_gpout2
GPIO Muxing 2.
Definition clocks.h:30
@ clk_peri
Peripheral clock for UART and SPI.
Definition clocks.h:34
@ clk_gpout1
GPIO Muxing 1.
Definition clocks.h:29
@ clk_ref
Watchdog and timers reference clock.
Definition clocks.h:32
@ clk_sys
Processors, bus fabric, memory, memory mapped registers.
Definition clocks.h:33
@ clk_usb
USB clock.
Definition clocks.h:35
@ clk_gpout3
GPIO Muxing 3.
Definition clocks.h:31
@ clk_adc
ADC clock.
Definition clocks.h:36
Definition clocks.h:43
Definition clocks.h:66
Definition clocks.h:129
Definition clocks.h:79