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rosc.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
3/*
4 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _HARDWARE_STRUCTS_ROSC_H
10#define _HARDWARE_STRUCTS_ROSC_H
11
13#include "hardware/regs/rosc.h"
14
15// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rosc
16//
17// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
18// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h.
19//
20// Bit-field descriptions are of the form:
21// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
22
23typedef struct {
24 _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL
25 // Ring Oscillator control
26 // 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to ENABLE
27 // 0x00000fff [11:0] : FREQ_RANGE (0xaa0): Controls the number of delay stages in the ROSC ring
28 io_rw_32 ctrl;
29
30 _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA
31 // The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage
32 // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings
33 // 0x00007000 [14:12] : DS3 (0): Stage 3 drive strength
34 // 0x00000700 [10:8] : DS2 (0): Stage 2 drive strength
35 // 0x00000070 [6:4] : DS1 (0): Stage 1 drive strength
36 // 0x00000007 [2:0] : DS0 (0): Stage 0 drive strength
37 io_rw_32 freqa;
38
39 _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB
40 // For a detailed description see freqa register
41 // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings
42 // 0x00007000 [14:12] : DS7 (0): Stage 7 drive strength
43 // 0x00000700 [10:8] : DS6 (0): Stage 6 drive strength
44 // 0x00000070 [6:4] : DS5 (0): Stage 5 drive strength
45 // 0x00000007 [2:0] : DS4 (0): Stage 4 drive strength
46 io_rw_32 freqb;
47
48 _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT
49 // Ring Oscillator pause control
50 io_rw_32 dormant;
51
52 _REG_(ROSC_DIV_OFFSET) // ROSC_DIV
53 // Controls the output divider
54 // 0x00000fff [11:0] : DIV (0): set to 0xaa0 + div where
55 io_rw_32 div;
56
57 _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE
58 // Controls the phase shifted output
59 // 0x00000ff0 [11:4] : PASSWD (0): set to 0xaa
60 // 0x00000008 [3] : ENABLE (1): enable the phase-shifted output
61 // 0x00000004 [2] : FLIP (0): invert the phase-shifted output
62 // 0x00000003 [1:0] : SHIFT (0): phase shift the phase-shifted output by SHIFT input clocks
63 io_rw_32 phase;
64
65 _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS
66 // Ring Oscillator Status
67 // 0x80000000 [31] : STABLE (0): Oscillator is running and stable
68 // 0x01000000 [24] : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or...
69 // 0x00010000 [16] : DIV_RUNNING (0): post-divider is running
70 // 0x00001000 [12] : ENABLED (0): Oscillator is enabled but not necessarily running and stable
71 io_rw_32 status;
72
73 _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT
74 // This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or...
75 // 0x00000001 [0] : RANDOMBIT (1)
76 io_ro_32 randombit;
77
78 _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT
79 // A down counter running at the ROSC frequency which counts to zero and stops
80 // 0x000000ff [7:0] : COUNT (0)
81 io_rw_32 count;
82} rosc_hw_t;
83
84#define rosc_hw ((rosc_hw_t *)ROSC_BASE)
85
86#endif
Definition rosc.h:23