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scb.h
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/*
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_SCB_H
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#define _HARDWARE_STRUCTS_SCB_H
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#include "
hardware/address_mapped.h
"
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#include "hardware/regs/m0plus.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
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typedef
struct
{
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_REG_(M0PLUS_CPUID_OFFSET)
// M0PLUS_CPUID
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// Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor...
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// 0xff000000 [31:24] : IMPLEMENTER (0x41): Implementor code: 0x41 = ARM
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// 0x00f00000 [23:20] : VARIANT (0): Major revision number n in the rnpm revision status:
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// 0x000f0000 [19:16] : ARCHITECTURE (0xc): Constant that defines the architecture of the processor:
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// 0x0000fff0 [15:4] : PARTNO (0xc60): Number of processor within family: 0xC60 = Cortex-M0+
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// 0x0000000f [3:0] : REVISION (1): Minor revision number m in the rnpm revision status:
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io_ro_32 cpuid;
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_REG_(M0PLUS_ICSR_OFFSET)
// M0PLUS_ICSR
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// Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending...
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// 0x80000000 [31] : NMIPENDSET (0): Setting this bit will activate an NMI
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// 0x10000000 [28] : PENDSVSET (0): PendSV set-pending bit
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// 0x08000000 [27] : PENDSVCLR (0): PendSV clear-pending bit
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// 0x04000000 [26] : PENDSTSET (0): SysTick exception set-pending bit
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// 0x02000000 [25] : PENDSTCLR (0): SysTick exception clear-pending bit
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// 0x00800000 [23] : ISRPREEMPT (0): The system can only access this bit when the core is halted
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// 0x00400000 [22] : ISRPENDING (0): External interrupt pending flag
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// 0x001ff000 [20:12] : VECTPENDING (0): Indicates the exception number for the highest priority pending exception: 0 =...
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// 0x000001ff [8:0] : VECTACTIVE (0): Active exception number field
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io_rw_32 icsr;
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_REG_(M0PLUS_VTOR_OFFSET)
// M0PLUS_VTOR
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// The VTOR holds the vector table offset address
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// 0xffffff00 [31:8] : TBLOFF (0): Bits [31:8] of the indicate the vector table offset address
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io_rw_32 vtor;
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_REG_(M0PLUS_AIRCR_OFFSET)
// M0PLUS_AIRCR
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// Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state...
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// 0xffff0000 [31:16] : VECTKEY (0): Register key:
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// 0x00008000 [15] : ENDIANESS (0): Data endianness implemented:
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// 0x00000004 [2] : SYSRESETREQ (0): Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be...
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// 0x00000002 [1] : VECTCLRACTIVE (0): Clears all active state information for fixed and configurable exceptions
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io_rw_32 aircr;
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_REG_(M0PLUS_SCR_OFFSET)
// M0PLUS_SCR
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// System Control Register
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// 0x00000010 [4] : SEVONPEND (0): Send Event on Pending bit:
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// 0x00000004 [2] : SLEEPDEEP (0): Controls whether the processor uses sleep or deep sleep as its low power mode:
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// 0x00000002 [1] : SLEEPONEXIT (0): Indicates sleep-on-exit when returning from Handler mode to Thread mode:
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io_rw_32 scr;
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}
armv6m_scb_t
;
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#define scb_hw ((armv6m_scb_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET))
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#endif
address_mapped.h
armv6m_scb_t
Definition
scb.h:23